发明名称 LOGIC SIMULATOR
摘要 <p>PURPOSE:To deal with simulation mixing a function level and a gate level. CONSTITUTION:An input queue 11 stores an input from an event bus 7. A gate level evaluator 5 evaluate a gate level node based on the event of the input queue 11. A function level evaluator 6 evaluates a function level node. An input control circuit 12 extracts the event from the input queue and judges the class of that node. When the node to be evaluated is the gate level, the gate level evaluator 5 to evaluate the node of the gate level performs the evaluation and when the node to be evaluated is the node of the function level, the function level evaluator 6 to evaluate the node of the function level performs the evaluation. An output control circuit 10 monitors the evaluation end of the evaluator 5 and controls the output of data to an evaluation bus 8.</p>
申请公布号 JPH0644335(A) 申请公布日期 1994.02.18
申请号 JP19920066638 申请日期 1992.03.25
申请人 NEC CORP 发明人 NAKADA TOSHIYUKI
分类号 G06F11/25;G06F11/26;G06F17/50;G06F19/00 主分类号 G06F11/25
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