发明名称 FRAME PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To shorten the delay time of a frame phase synchronizing circuit in the condition that bits are synchronized between input and output with respect to the transmission frame having the numerical value (pointer), which indicates the head position of a payload, in the overhead part. CONSTITUTION:A reception pointer value 12 is obtained by a pointer interpreting part 4, and the phase difference (offset pointer value 14) in the payload head position between input and output frames is obtained by an offset detecting part 6, and a substitution pointer value 15 is obtained from the sum of the reception pointer value 12 and the offset pointer value 14 by an addition processing part 7, and thereby, only the phase difference of overhead between the input and the output is absorbed through a variable shift register 8 to deliver data with a minimum delay.
申请公布号 JPH0646023(A) 申请公布日期 1994.02.18
申请号 JP19920195703 申请日期 1992.07.23
申请人 NEC CORP;NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KOBAYASHI MASATO;UEMATSU HITOSHI;UEDA HIROMI
分类号 H04J3/06;H04J3/00;H04L7/08 主分类号 H04J3/06
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