发明名称 SIMULTANEOUS SWITCH LIMITTER
摘要 PURPOSE:To drop the level of noise so as to prevent the malfunction of a device by dividing data outputted to a data bus in the unit of one bit or plural bits by means of a control signal delayed into plural stages and fetching data into a data holding part. CONSTITUTION:A data latch part 2 fetches a data signal 10 which a main body control part generates by the control signal 11 so as to latch it, and outputs it as a data signal 20. A data maintenance control signal delay part 4 delays the control signal 11 by different time by delay elements 41 and 42 and gives the instruction of three kinds of timing to the data latch circuits 51-59 of the data holding part 5 with the control signal as a control signal 40. Thus, the signals of all bits in data signals, 50 which the data holding part 5 outputs do not simultaneously change. When the data signal 50 is outputted to the data bus, noise occurring in the data bus can be reduced by the simultaneous switching of the signal levels.
申请公布号 JPH0644149(A) 申请公布日期 1994.02.18
申请号 JP19920099103 申请日期 1992.04.20
申请人 NEC CORP 发明人 YOSHIOKA SADAO
分类号 G06F3/00;G06F13/00;G06F13/36 主分类号 G06F3/00
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