| 摘要 |
PURPOSE:To prevent generation of a counter error by adding a pulse superposition detecting circuit and detecting a pulse superposition between UP and DOWN clocks. CONSTITUTION:The pulse width values of UP and DOWN clocks 1, 2 are respectively converted by one period of a system clock 8 with respective differentiation circuits consisting of FF circuits 21, 22 and gate circuits 23, 24. When the clocks 1, 2 are allowed to pass through gates 26, 27, their pulse width is converted by a half period of the clock 8 and the converted clocks 1, 2 are inputted to a counting part. Thus, when the rise of the clocks 1, 2 are differentiated due to the overlap of their L levels, the superposition of the clocks 1, 2 is canceled after their differentiation and the clocks 1, 2 can be normally counted. When the L levels of the clocks 1, 2 are superposed and the clocks 1, 2 are simultaneously raised, the output 7 of a gate 25 is turned to an 'H' level, the gates 26, 27 are closed and their counting is held at a stopped state. Thereby even when UP and DOWN clocks are asynchronously inputted, the generation of a counting error can be prevented. |
