| 摘要 |
PURPOSE: To easily test a digital system by connecting memory elements interconnected with a composite network in normal operation mode, to include a plurality of scanning chains in scanning mode. CONSTITUTION: When a test stimulus pattern 63 is loaded to scanning chains 30-50 at the time of scanning test, the chains 30-50 are reconfigured in a normal operation mode during one clock cycle at each clock rate of the chains 30-50, by a mode selection signal from a configuration controller 62. During that interval, the test stimulus pattern 63 is applied to a composite network 20, and the date stored in the memory element of each chain 30-50 is altered. Subsequently, the controller 62 applies the mode selection signal to a mode selection bus 82 to reconfigure the memory elements in the scanning mode, and a test response pattern is clocked from the chains 30-50 between the subsequent clock cycles. The test response pattern is clocked to a test response processor 64 and delivered through a tap 70 to an external tester. |
