| 摘要 |
PURPOSE:To provide the semiconductor memory device capable of improving the relief efficiency using the ECC system. CONSTITUTION:A memory cell array (600) is divided into plural small areas in column and row directions. In reading data, one bit memory cell is selected from the small areas arranged on different columns and rows in the array. The data read concurrently contain information bit and error check bit. Accordingly, the only data of one-bit memory cell are read out of one word line. Even though one word line fails, the possibility of the number of error bits contained in plural bit data concurrently read out being more than 2 bits can be reduced remarkably. Thus, the error detection and correction using the ECC system can be executed and the relief efficiency of the fault bit can be improved. |
