| 摘要 |
PURPOSE: To obtain a phase/frequency comparator that employs a charge pump PLL, without a parasitic pulses by connecting respectively the inputs of 1st and 2nd AND gates to outputs of 2nd and 1st NAND gates. CONSTITUTION: Suppose that the trailing edge of a signal fA is produced and a output A goes to O, even when a gate 32 goes to '1' until a succeeding trailing edge of a signal fB, the gate 32 remains at a level '0'. Then an output B remains at a level '1'. When the output A goes to '1' after switching of a gate 20, a level '1' of a gate 15 is fed to a gate 18 and a parasitic pulse at the output B is suppressed for a switching time of the gate 20. When a leading edge of the signal fB is produced and the output B goes to '0', and when a gate 14 goes to '1' till a succeeding trailing edge of the signal fA, the gate 30 remains at '0'. Then the output A remains at '1' and when the output B goes to '1' after switching of the gate 20, the level '1' of the gate 14 is fed to a gate 17. Then the parasitic pulses at the output A is suppressed for the period of switching of the gate 20. |
