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发明名称
DESIGNING METHOD FOR LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要
申请公布号
JPH0645444(A)
申请公布日期
1994.02.18
申请号
JP19920197021
申请日期
1992.07.23
申请人
TOSHIBA CORP
发明人
ISHIOKA TAKASHI
分类号
H01L21/82;G06F17/50;(IPC1-7):H01L21/82;G06F15/60
主分类号
H01L21/82
代理机构
代理人
主权项
地址
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