发明名称 Serial data bus system for communication between electronic modules - has bidirectional data and clock bus lines and parallel interruption bus allowing transmission from slave stations to master station
摘要 The bus system has two parallel bidirectional lines (5, 6) respectively used as a data bus and a clock bus for communication between a master station (1), acting as the data transmitter and a number of slave stations (2,3,4), acting as data receivers. The clock bus is coupled to a clock generator with a frequency which determines the data rate of the data transmitted via the data bus. A third parallel line acts as an interrupt bus (7) allowing the slave stations to transmit an interrupt signal to the master station, allowing data from the slave signal to be received by the latter. USE/ADVANTAGE - Rapid data communication between master and slave electronic modules by simple construction.
申请公布号 DE4226876(A1) 申请公布日期 1994.02.17
申请号 DE19924226876 申请日期 1992.08.13
申请人 ROHDE & SCHWARZ GMBH & CO KG, 81671 MUENCHEN, DE 发明人 MUELLER, JUERGEN, DIPL.-ING., 8000 MUENCHEN, DE
分类号 G06F13/42;H04L12/40;(IPC1-7):H04L12/40 主分类号 G06F13/42
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