| 摘要 |
<p>A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (30) on surface (28) patterns areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of thickness (52) contact layer (30). Trench (50) in areas (46) has sidewalls aligned to spacer surfaces (47) and extending depthwise through P-body layer (26) to depth (56). Oxide (60) on the trench walls and gate polysilicon (62) refills trench (50) to level (64) near surface (28). Oxide (68) between spacers (44) covers polysilicon (62). Removing layer (30) exposes surface (28') between surfaces (48). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to surfaces (48). Trench (80) defines vertically-oriented source and body layers (86, 90) stacked along oxide layer (60) to form vertical channels on opposite sides of trench (80). Layers (86, 90) have a lateral thickness (88) of the sidewall spacers. Conductor (94) contacts the N-source and P-body layers, and an enhanced P+ region in trench (80).</p> |
