| 摘要 |
The demodulator is basically constituted by mixers (2) and (3), low pass filters (LPFs) (4) and (5), A/D converters (6) and (7), a clock recovery circuit (8), a phase error detecting circuit (9), a digital-to-analog (D/A) converter (10), a loop filter (11), a voltage adder (12), a sweep controller (13 min ), a voltage controlled oscillator (VCO) (14), a 90 DEG phase shifter (15), and an error correction/synchronization decision circuit (16). Connected between the sweep controller (13 min ) and the D/A converter (10) are a high pass filter (HPF) (101), a detector (102), and a comparator (103). The error correction/synchronization decision circuit (16) determines whether synchronization has been established, whereupon the sweep controller (13 min ) stops generating a sweep signal and holds its output at a predetermined level. In the event of false synchronization, a beat component is superposed on the output (error voltage) of the D/A converter (10). The detector (102) detects the input beat component signal. Receiving an output of the detector (102), the comparator (103) compares the output of the detector (102) with a predetermined reference voltage. When the output of the detector (102) is higher than the reference voltage, the comparator (103) feeds the previously mentioned control signal to the sweep controller (13 min ) . As a result, the sweep controller (13 min ) resumes the generation of a sweep signal, i.e., the false synchronization is cancelled. |
