发明名称 SINGLE CLOCK CYCLE DATA COMPRESSOR/DECOMPRESSOR WITH A STRING REVERSAL MECHANISM
摘要 <p>A single clock cycle adaptive data compressor/decompressor (1/2) with a string reversal mechanism (6) is described which can perform data compression and decompression at the rate of one uncompressed symbol per clock cycle. The compressor (1) builds a string table as the data is received. Each string within the table is made up of the address within the table of the longest previously seen matching string and the one character that makes this string different. This data compressor/decompressor (1/2) utilizes a content addressable memory (4) to store the string table. This content addressable memory (4) allows the compressor (1) to store the current symbol string in a table while that same string table is simultaneously searched for the current string. During decompression the characters within a symbol string are output in reverse of the order in which they were input. Two dual-ported random-access memories (7, 8) are used as circular queues to perform string reversal.</p>
申请公布号 WO1994003983(A1) 申请公布日期 1994.02.17
申请号 US1993007114 申请日期 1993.08.02
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