| 摘要 |
A static RAM cell in which the load devices are moved from the state nodes to outer nodes of a cross-coupled pair of transistors in first and second driver elements (33 and 35). Each driver element has a first (T1A or T3A) and a second (T1 or T3) transistor and a resistive device (42 or 44). Each transistor has first, second and third terminals, with the second terminals being the input terminals. A first terminal of the first transistor (T1A) of the first driver element (33) is connected to the resistive element (42) at a first node. A first terminal of the first transistor (T3A) of the second driver element is connected to the resistive element (44) at a second node. A first terminal of the second transistor (T1) of the first driver element (33) is connected to the resistive device (42) at a third node. A first terminal of the second transistor (T3) of the second driver element is connected to the resistive device (44 ) at a fourth node. The input terminals of the first and second transistors (T1A and T1) of the first driver element (33) are connected to the second node and the input terminals of the first and second transistors (T3A and T3) of the second driver element (35) are connected to the first node. The third terminals of the first and second transistors of the first and second driver elements are connected to a first source of common potential. A first load device (26) is connected to a second source of common potential on one end and is connected to the third node on a second end. Likewise, a second load device (28) is connected to the second source of common potential on one end and to the fourth node on the second end.
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