| 摘要 |
A circuit (400) is added to a complementary metal-oxide silicon integrated circuit to provide an intentional, non-reverse-biased VDD-to-VSS shunt path for transient currents such as electrostatic discharges. This circuit protects the IC from ESD damage by turning on before any other path, thus directing the ESD transient current away from easily damage structures. Specifically, the ESD transient current is steered from the VDD rail (102) to the VSS rail (101) through the on conduction of a P-channel transistor (P3) whose source and drain are connected to VDD and VSS respectively. The voltage on the gate of this transistor follows the VDD supply rail because it is driven by a delay network formed by a second transistor (P4) and a capacitor (C1). This VDD-tracking delay network turns the VDD-to-VSS transistor on during a transient and off during normal operation of the IC.
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