Clock generators having programmable fractional frequency division

摘要

A clock generator is described for generating an output clock frequency from an input clock frequency where the frequencies of the clocks are not integrally related. The division process is designed using the quotients of the Euclidean theorem for determining the greatest common divisor of two integers in such a way as to alleviate the adverse effects of jitter. Applications to oversampled sigma-delta codecs are described.