| 发明名称 |
DMA controller using a programmable timer, a transfer counter and an or logic gate to control data transfer interrupts |
| 摘要 |
A DMA controller interrupts data transfer as needed to transfer the bus use permit to the CPU and resumes data transfer when the CPU completes the memory use in the burst mode in which the predetermined number of words is transferred between the I/O device and the memory.
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| 申请公布号 |
US5287486(A) |
申请公布日期 |
1994.02.15 |
| 申请号 |
US19930065511 |
申请日期 |
1993.05.20 |
| 申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
YAMASAKI, TAKASHI;KURODA, SACHIE |
| 分类号 |
G06F13/28;(IPC1-7):G06F12/00;G06F13/00 |
主分类号 |
G06F13/28 |
| 代理机构 |
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代理人 |
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| 主权项 |
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