Dynamic PLA time circuit

摘要

A dynamic PLA timing circuit in a PLA ROM includes a PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address lines and the address section of the other PLA line is connected to the complementary address lines. Shorting bars connecting the two PLA lines are formed around each pair of true and complementary address lines such that a conductive path is formed through the address sections for any address into the ROM. The data section is connected to the gates of every data transistor. However, the drains of all but one of the data transistors are not connected to their associated data line. The data line that is connected to the associated data transistor forms the output terminal of the timing circuit.