发明名称 |
Memory cell circuit and array |
摘要 |
An improved memory cell (118) is provided which may be incorporated into an array (202) of memory cells. Array (202) includes a first gate conductor region (224) and a second gate conductor region (238), wherein the first and second gate conductor regions are orthogonal to one another. Each one-half of the cell may include two series transistors connected to a cross-coupled trench transistor. Cross-coupling of the trench transistors is effected through the use of parallel local interconnect regions (256) and (258).
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申请公布号 |
US5287304(A) |
申请公布日期 |
1994.02.15 |
申请号 |
US19900636518 |
申请日期 |
1990.12.31 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
HARWARD, MARK G.;MAHANT-SHETTI, SHIVALING S.;TIGELAAR, HOWARD |
分类号 |
G11C11/402;G11C11/412;H01L27/10;(IPC1-7):G11C13/00 |
主分类号 |
G11C11/402 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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