| 摘要 |
A multiport DRAM having a DRAM cell array; a sequential access memory (SAM) for inputting data of a specific length to the DRAM cell array and transmitting that data to an external device; a SAM address counter for counting the addresses of the data in the SAM; a serial port connected to the SAM for transmitting the data in the SAM to an external device; a data transfer address counter, the contents of which is cleared by inputting an external reset signal and is counted up by inputting an overflow signal which is output from the SAM address counter; and a data transfer controller for outputting a data transfer status signal which indicates that data transmission is in progress when data of a specific length in the DRAM cell array designated by the input of the overflow signal by the data transfer address counter is transmitted to the SAM.
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