| 摘要 |
A solid state, reverse power flow detector and control circuit which samples the line voltage and current, once each cycle. The voltage sampling circuit includes a pulse generator providing a voltage pulse of short duration at a given time or phase angle in each cycle. The voltage signals are applied to an SCR through a gate operated by the current signals. In one embodiment, the gate comprises a single transistor. With forward or no current, the gate does not allow the voltage signals to reach the SCR. When current reverses, the gate allows the voltage signals to trigger the SCR. The SCR turns on a transistor energizing a relay, after a brief delay. The relay acts to set the regulator or other device in power reverse condition. When current again is forward, the relay is deenergized and the device returned to the forward condition.
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