发明名称 |
Integrated circuit chip having primary and secondary random access memories for a hierarchical cache |
摘要 |
A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits which include all of the interconnecting data lines. Each integrated circuit includes a primary memory and a secondary memory for storing and retrieving data transferred over a first data input line and a first data output line that link the primary memory to a central processing unit. At any given time, a multi-bit word is addressed in the secondary memory, and a corresponding multi-bit word is addressed in the primary memory. The primary and secondary memories are interconnected by a first multi-line bus for transferring a multi-bit word read from the secondary memory to the primary memory, and by a second multi-line bus for transferring a multi-bit word read from the primary memory to the secondary memory. The secondary memory is linked to a main memory by a second data output line and a second data input line for sequential transmission of bits to exchange multi-bit words during a writeback and refill operation. In a preferred embodiment, data inputs of the primary memory and the secondary memory are wired in parallel to a serial-parallel shift register that is used as a common write buffer.
|
申请公布号 |
US5285323(A) |
申请公布日期 |
1994.02.08 |
申请号 |
US19930061273 |
申请日期 |
1993.05.13 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
HETHERINGTON, RICKY C.;MCKEEN, FRANCIS X.;MARCI, JOSEPH D.;FOSSUM, TRYGGVE;EMER, JOEL S. |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|