| 摘要 |
PURPOSE:To secure the shorter output emerging time due to the set or reset input by forming the flip-flop through the wired OR connection of the two negative logic via two units of the double input positive logic NAND gate each. CONSTITUTION:First logic circuit 23 is formed with two double input positive logic NAND gates 24 and 25 which receive the wired OR connection of the negative logic to each other. And the second logic circuit 26 is formed with double input positive NAND gates 27 and 28. And the flip-flop is formed with these two logic circuits 23 and 26. Both forward phase reset pulse R and beackward phase set pulses # are applied to circuit 23; while backward phase reset pulse # and forward phase set pulse S are applied to circuit 26 each. As a result, the time during which output Q and # emerge after the set or reset input applied can be reduced down to 1/2 the conventional time. |
