| 摘要 |
<p>PURPOSE: To attain a higher processing speed for the synchronous digital logic circuit that has memory elements whose state is controlled while each having a clock input terminal and at least two complementary output terminals and at least two input terminals connecting to a OR logic element. CONSTITUTION: In the digital logic circuit, at least two memory elements 10, 11 are connected in cascade, and the 1st memory element 10 conducts OR arithmetic operation and the 2nd memory element 11 executes AND arithmetic operation with one combined logic function. Thus, the set time of the memory elements and a delay time for OR and AND arithmetic operations are made in matching with each other.</p> |
