| 摘要 |
PURPOSE: To provide a fault tolerant computer system including plural central processing units. CONSTITUTION: Each CPU is provided with a cache memory 33 and a parity error detector 34 which detects a parity error in a block of read/write information. A system bus 2 connects CPUs to an SCU(system control unit) having a parity error correction function and a memory bus connects the SCU to a main memory. An error recovery control function transfers a faulty block from the CPU on the sending side to a main memory through the SCU (where the given faulty block is corrected) in response to detection of a read parity error on the sending side and a write parity error in the CPU on the reception side in relation to siphon operation; and thereafter, the corrected memory block is transferred from the main memory to the CPU on the reception side at the time of retry. |
