发明名称 |
METHOD FOR REDUCTION OF SPURIOUS SIGNAL GENERATED BY DIGITAL SIGNAL PROCESSOR |
摘要 |
PURPOSE: To reduce spurious signals which are produced by changes of power consumption due to the cyclic operation of a processor. CONSTITUTION: A digital signal processor that depends on a command code to be executed carries out a circulatively repeated program routine BP which is initialized by an interrupt INT. A 1st mean power consumption Im is produced for an operation time, and the operating time, which is shorter than a time between two continuous interrupts, of the routine BP is produced by power consumption of the digital signal processor. The processor performs a waiting routine AWAIT that produces mean power consumption of the processor which corresponds to the consumption Im in the program routine period between continuous program routines BP. |
申请公布号 |
JPH0629842(A) |
申请公布日期 |
1994.02.04 |
申请号 |
JP19930099857 |
申请日期 |
1993.04.26 |
申请人 |
DEUTSCHE ITT IND GMBH |
发明人 |
TOOMASU HIRUPAATO;SHIYUTEFUAN MIYURAA;YURUGEN BETSUHIYAA;BIRUFURIITO BERUNAA GEERITSUHI |
分类号 |
H03M1/08;G06F11/00;G06J1/00;(IPC1-7):H03M1/08 |
主分类号 |
H03M1/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|