| 摘要 |
PURPOSE:To eliminate a phase error component generated due to frequency offset and fading. CONSTITUTION:A digitally phase-modulated signal is inputted to an input terminal 1, and the amplitude of an inputted signal is converted to a logic level by a limiter 2. Meanwhile, the count value of a counter 5 counted based on a clock signal from an oscillator 3 is held with a latch circuit 6 replying to the output signal of the limiter 2, and the output of the latch circuit 6 is delayed by a time of one symbol interval by a delay circuit 7, and subtraction between the output of the latch circuit 6 and that of the delay circuit 7 is performed by a subtractor circuit 8, then, phase change data is outputted. Phase compensation is applied to such phase change data by a phase compensation circuit 10, and a decoder circuit 12 reproduces the data. |
