发明名称 Configurable logic cell for field programmable gate array - has device for performing combinational logic function coupled to device which is set to operate as D=type or toggle flip=flop
摘要 The logic cell (1) has inputs (4) and at least one output (5). The logic cell includes a device (2), e.g. a look-up table, whose inputs are connected to the inputs (4) of the logic cell. A second device (3), a flip-flop, has its single input connected to the output of the first device and its output coupled to the logic cell output terminal. The first device performs a desired combinational logic function. The second device stores a data value and can be set to operated either as a D-type flip-flop or as a toggle flip-flop. ADVANTAGE - Simplifies circuit for realising sequential logic, e.g. for counter or state machine.
申请公布号 DE4224805(A1) 申请公布日期 1994.02.03
申请号 DE19924224805 申请日期 1992.07.27
申请人 SIEMENS AG, 80333 MUENCHEN, DE 发明人 BECKER, STEFFEN, DIPL.-ING., O-6300 ILMENAU, DE;KEITEL-SCHULZ, DORIS, DIPL.-ING., 8000 MUENCHEN, DE;SCHMITT-LANDSIEDEL, DORIS, DR.RER.NAT., 8012 OTTOBRUNN, DE
分类号 H03K19/173;(IPC1-7):H03K19/00;H03K23/00 主分类号 H03K19/173
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