Semiconductor memory device with an error checking and correcting circuit.

摘要

A semiconductor memory device comprises: a memory cell array partitioned into a plurality of sub cell arrays (100A-D), each of the sub cell arrays (100A-D) having both normal memory cells and parity cells; a plurality of sense amplifier groups (110A-D) each being connected to one of the sub cell arrays (100A-D), for performing sensing operation of cell data from the sub cell arrays (100A-D); a plurality of error checking and correcting circuits (130A-D) each being connected to one of the sense amplifier groups (110A-D) via a respective latch circuit (120A-D), for repairing syndrome bits within the cell data; and output decoders (140A-D) each being connected to an output of one of the error checking and correcting circuits (130A-D). When the semiconductor memory device is to be operated in a normal mode only one of the sub cell arrays (100A-D) is selected, and when the semiconductor memory device is to be operated in a page mode all of the sub cell arrays (100A-D) are selected. This can provide a useful saving of power consumption in normal mode. <IMAGE>