摘要 |
<p>FIR filter circuitry for processing time division multiplexed sampled signals includes parallel sets of delay elements (DSP, DHP), for delaying respective signals to be filtered, each set having a plurality of taps. Corresponding taps of the respective sets of delay elements are coupled to common weighting (Wn+i) and summing structure (Adder). A time division multiplexed signal is coupled to the parallel sets of delay elements, respective sets being exclusively (Dsp Clk, Dhp Clk) clocked on the occurrence of corresponding signals. <IMAGE></p> |