COMPUTER SYSTEM CLOCK GENERATOR

摘要

COMPUTER SYSTEM CLOCK GENERATOR A computer system clock generator for generating several clock signals which are in a tuned state at desired locations, thereby offsetting the effects of varying propagation delays among the system clock signals. A shift register ring has one of its taps selectively connected to its data input so that a series of logic high level and logic low level data is advanced through the shifting stages. A tap combines the signals for each desired output from the appropriate taps to produce output clock signals having desired leading and trailing edges.