发明名称 |
Analog voltage subtracting circuit and an A/D converter having the subtracting circuit |
摘要 |
An analog voltage subtracting circuit for calculating a difference between an analog input voltage and a voltage drop caused by a load includes an analog voltage generator 7 for generating an analog voltage, a load 3 having one end connected to an output of the analog voltage generator 7 and the other end connected to an output terminal 2, and a D/A converter 6 applying a positive output current Iout for generating a desired voltage drop at said the other end 4 of the load 3 and for applying a complementary output current I(OVS) complementary to the positive output current Iout to said one end of the load 3. By this structure, a constant current of Iout+I(OVS) flows at said one end 4 of the load 3, and therefore linear output can be provided.
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申请公布号 |
US5283581(A) |
申请公布日期 |
1994.02.01 |
申请号 |
US19920952413 |
申请日期 |
1992.09.29 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MIKI, TAKAHIRO;KUMAMOTO, TOSHIO |
分类号 |
H03M1/14;G06G7/14;H03M1/16;H03M1/74;(IPC1-7):H03M1/14 |
主分类号 |
H03M1/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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