| 摘要 |
<p>PURPOSE:To provide an economical frame synchronization protecting circuit by using each counter means to count the pulses included in a frame, to count the front protection stages, and to count the rear protection stages respectively. CONSTITUTION:A 1st counter means 2 counts the pulses included in a frame based on the signal of a control means 1 and outputs the final pulse. A 2nd counter means 3 refers to plural signals which show the state of a synchronization protecting circuit and the signal showing the detection of a synchronizing signal and counts the rear or front protection stages. Then a synchronizing state or an out-of-synchronization state is displayed when a prescribed number of stages are counted.</p> |
