| 摘要 |
PURPOSE:To reduce the power consumption and to reduce the circuitry by producing a clock signal in synchronism with a baseband signal and being a symbol rate frequency and thereby operating a delay section and an arithmetic section. CONSTITUTION:An input signal is synchronously detected by a quasi-synchronous detection circuit 2. The obtained common mode detection output X and orthogonal detection output Y are passed to a low-pass filter section 3, providing a baseband signal. An A/D conversion section 4 performs the sampling of the baseband signal by the frequency 32 multiple of a symbol rate frequency (f) and performs A/D conversion by a quantization bit 6. A/D-converted digital data Xk and Yk are inputted to a data delay section 5 and to a clock generation section 8. The delay section 5 outputs the data Xk and Yk and data Xk-1 and Yk-1 delayed by one time slot to an arithmetic section 6. The arithmetic section 6 accepts the clock frequency of the frequency (f), restoring I and Q signals being orthogonally crossed. A discrimination section 7 demodulates the common mode and orthogonal signals by means of the frequency 2f, outputting data. |
