发明名称 DELAY CIRCUIT
摘要 <p>PURPOSE:To reduce the total power consumption of a delay circuit by connecting in parallel plural delay element trains that include plural stages of delay elements connected in series. CONSTITUTION:A delay element train 25 includes a delay element 21 of delay time T set at the head of the train and the delay elements 22-24 of delay time 2T set on the following stages which are connected in series. Meanwhile, a delay element train 29 includes the delay elements 26-28 of delay time 2T connected in series to each other. These two trains 25 and 29 are connected in parallel to each other. Then, the delay output signals S1-S7 are selectively outputted through the output terminal of the elements 21-24 and 26-28 respectively. In such a constitution, the delayed output signals are acquired with extremely reduced power consumption.</p>
申请公布号 JPH0621761(A) 申请公布日期 1994.01.28
申请号 JP19920196012 申请日期 1992.06.30
申请人 SONY CORP 发明人 MURAKAMI DAISUKE;MATSUMOTO ISAO;KOBAYASHI KENJI;YOSHIDA HIDEKI
分类号 H03H11/26;G11C11/407;G11C11/4076;H03K5/13;(IPC1-7):H03H11/26 主分类号 H03H11/26
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