| 摘要 |
PURPOSE:To make it possible to rapidly integrate input data by controlling the counting operation of plural up/down counters, accumulatively adding input data and integrating the added results. CONSTITUTION:This digital integration circuit is provided with an N-bit full adder(FA) 101 for accumulatively adding input data, an N-bit delay (D-FF) 102 for delaying the output data of the FA 101 by time corresponding to a sampling period and supplying the delayed result to the FA 101, plural up/down counters(U/Di) cascade connected with each other, and an arithmetic circuit (GATE) 103 for controlling the counting operation of plural U/Di based upon the most significant bit(MSB) of input data, the MSB of output data from the FA 101, the MSB of output data from the D-FF 102 and the carry output of the FA 101. When N-bit input data are inputted, the FA 101 adds the input data to accumulatively added value obtained before one-sampling time which is added in the D-FF 102, supplies the accumulatively added value to the D-FF 102 and supplies a carry output to the GATE 103. |
