| 摘要 |
PURPOSE:To accelerate the rise time or fall time of output as suppressing power consumption. CONSTITUTION:A CMOS inverter is provided as shown in figure (a), and when the input Vi of the inverter is reset to intermediate potential between high potential equivalent to logic H and low potential equivalent to logic L, output Vo is connected to the power source line Vss of potential equivalent to the logic L. An N-channel MOS transistor N10 which comprises the CMOS inverter is connected to a resistance element Z10 in series. Also, in a logical gate equipped with a CMOS inverter shown in figure (b), the output Vo is connected to the power source line Vcc of potential equivalent to the logic H when the input Vi of the inverter is reset to the intermediate potential between the high potential equivalent to the logic H and the low potential equivalent to the logic L. A P-channel MOS transistor P20 which comprises the CMOS inverter is connected to a resistance element Z20 in series. |
