| 摘要 |
PURPOSE:To enable the emulation for a high-speed and multifunctional microprocessor by switching the state of a bus so that a specified space is operated at low speed when a break occurs. CONSTITUTION:When a break interruption signal/BRK is received from a break detection circuit, a CPU 21 switches a system from a user space to a system space, and outputs a break acknowledge signal/BREAK to an external part. In such a case, the area of an emulation memory including a restart address becomes a three state cycle in the system space. Thus, the connection of a low speed memory becomes possible. Then, emulation control in a break interruption processing becomes possible. The system space is set to be only an access cycle by CPU 21 and the access of a DMA controller 25 and a DRAM refresh controller 26 is set to be the user space. Thus, DMA transfer/DRAM refresh functions normally operate. |
