Huffman decoder architecture for high speed operation and reduced memory.

摘要

The speed of decoding a Huffman coded signal such as a still, moving or high definition image signal, is increased by memory efficient architectures. The coded signal contains coded units, each of which represents a block of pixels and comprises token bits (which define at least the length of the coded unit) and mantissa bits (of variable number). A shift register 24 holds a number of bits from, on average, a plurality of coded units, and each cell of the shift register is connected to an input of a memory 30 or look-up table to decode simultaneously the plurality of tokens. The total bit length of the coded units represented by the valid tokens is fed back to the shift register to feed through a whole number of coded units. This permits simultaneous decoding of a plurality of variable length coded units.