发明名称 |
Synchronization circuit |
摘要 |
A synchronization circuit for ATM cells transferred in an ATM communication system, wherein the synchronization circuit receives and holds in a bit serial manner the input bit trains constituting the received ATM cells by a shift register unit, performs a CRC operation in a bit serial manner on the held input bit trains by a continuous CRC arithmetic unit in accordance with a simplified CRC operation process different from the usual CRC operation process, and performs the necessary synchronization control upon receiving the CRC arithmetic operation result at a synchronization control unit, thereby enabling CRC arithmetic operations to be performed continuously and by simple hardware on the headers in the ATM cells.
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申请公布号 |
US5282215(A) |
申请公布日期 |
1994.01.25 |
申请号 |
US19910672863 |
申请日期 |
1991.03.20 |
申请人 |
FUJITSU LIMITED |
发明人 |
HYODO, RYUJI;NISHINO, TETSUO;ISONO, OSAMU;TACHIBANA, TETSUO;MIYAMOTO, NAOYUKI;OOMURO, KATSUMI;YONETA, TSUYOSHI |
分类号 |
G06F11/10;H03M13/00;H04L7/00;H04L7/04;H04L7/08;H04L12/56;H04Q11/04;(IPC1-7):G06F11/10 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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