发明名称 |
Interrupt distribution scheme for a computer bus |
摘要 |
A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment is described. This method allows a multiple-tiered, increasing priority, interrupt request scheme. This method also allows processor to processor directed interrupt requests, processor to one processor of a group of processors interrupt requests, and processor to all processors of a group of processors interrupt requests.
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申请公布号 |
US5282272(A) |
申请公布日期 |
1994.01.25 |
申请号 |
US19930010486 |
申请日期 |
1993.01.28 |
申请人 |
INTEL CORPORATION |
发明人 |
GUY, CHARLES B.;CADAMBI, SUDARSHAN B.;GUTMANN, MICHAEL J.;BHASKER, NARJALA;TRETHEWEY, JIM R.;MCARDLE, BRIAN J. |
分类号 |
G06F9/48;(IPC1-7):G06F9/46 |
主分类号 |
G06F9/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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