Leading one anticipator and floating point addition/subtraction apparatus employing same

摘要

A floating point addition/subtraction apparatus is internally provided with a leading one anticipator having redundant binary numeral generators, intermediate-carry/intermediate-sum generators, and scan-value generators. Each of the redundant binary numeral generators performs a subtraction with respect to two binary operands, a binary minuend and a binary subtrahend, to generate a redundant binary numeral Zsd having "-1", "0" or "1" at each digit thereof. Each of the intermediate-carry/intermediate-sum generators generates an intermediate carry Ck and an intermediate sum Sk in accordance with Zsdk=2Ck+Sk using a redundant binary numeral Zsdk positioned at a kth digit from a least significant digit of the redundant binary numeral Zsd and a redundant binary numeral Zsdk+1 positioned at a (k+1)th digit so that Ck=Zsdk when Zsdk+1="1" or "-1" and Ck=0 when Zsdk+1="0". Each of the scan-value generators generates "1" (or "0") when a result of an addition with respect to an intermediate carry Ck-1 and the intermediate sum Sk is "0" and generates "0"(or "1") when the result of the addition is a numeral other than "0".