| 摘要 |
An EEPROM cell with a single level gate structure is structured over at least three distinct active areas of the semiconducting substrate over which extend portions of the single isolated gate structure of the cell. A read transistor of the cell is formed in a distinct active area which is substantially isolated from the active area of the select transistor, wherein the thin dielectric tunnel layer is formed. Therefore the interface toward the external logic circuitry represented by the read transistor and the interface toward the programming circuitry are substantially isolated from each other. The read transistor may be designated to function at voltage and current levels compatible with the operating levels of the logic circuitry without interfering with the programming of the cell, thus eliminating the need for level regenerating stages. A second complementary read transistor may be formed into a fourth distinct active area, suitably doped, thus providing a read interface structured as a normal CMOS inverter stage. The ability of the read transistor to operate at standard CMOS levels, makes the EEPROM cell particularly suited for implementing multiplexing or programmable interconnection arrays in CMOS devices.
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