Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for the timing optimization of multilevel logic

摘要

A process of realizing large scale integrated circuits by means of a programmed data processor includes minimizing timing delays in the technology mapping phase by employing algorithms which are based on a linear model in terms of number of inputs and a load capacitance of a gating function and which permit a decomposition of the gating function into gates having m inputs and ((n-m)+1) inputs wherein m is greater than two. Balanced decompositions may be allowed in appropriate conditions.