| 摘要 |
The system comprises sample and holders (2a,2b), A/D converters (3a,3b), coded interleave scrambles (4a,4b), 1st multiplexer (6), a parallel-serial converter (7), an interpolation control code generating circuit (11), 2nd multiplexer (9), an audio signal separation section (20), a data interpolator (29), a control code separator (21), a sample and holder (23), a data decoder (24), a serial- parallel converter (25), a field judging section (26), deinterleave descramble error correction sections (28a,28b), a data correction section (29), and D/A converters (30a,30b).
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