| 摘要 |
PURPOSE:To remove a clock skew generated between clock signals which are distributed on a circuit where plural processors processes information synchronously by using the clock signals of the same frequency. CONSTITUTION:The clock signals are not distributed directly, clock generators 2a-2c are arranged nearby the processors 3a-3c, and further a basic clock generator 1 which supplies a basic clock to the clock generators 2a-2c is provided. The clock signals which are varied in phase by adjusting the clock skew are outputted from plural outputs of the basic clock generator 1. Thus, the clock signals are actively varied in phase at the generation source for the clock signals and then the clock signals supplied to the processors 3a-3c can be put in phase at reception terminals. |
