| 摘要 |
PURPOSE:To reduce the number of patterns by eliminating redundant patterns at the time of expanding the pattern of a clock application timing form to that of a clock waveform input form with respect to simulation patterns of a logic circuit. CONSTITUTION:Pin clock information 3 is obtained from a logic circuit 1 by a pin information extracting means 2, A clock application timing form pattern 4 is read in by a pattern read means 5, and it is checked by a pattern confirming means 6 that the clock is turned off so that the clock pattern and the other input pattern do not contend with each other. After this check, the pattern 4 is expanded to a clock waveform input form pattern 8 by a single- phase clock pattern expanding means 7 and is used as the input pattern for simulation of the logic circuit 1 by a simulation means 9 to obtain an output expected value 10. |
