发明名称 CLOCK SUPPLY SYSTEM
摘要 PURPOSE:To supply a reference signal and a timing signal having a redundant system without a phase difference to a device by counting the phase difference between reference frequencies and between timing signals due to the phase error of two voltage controlled oscillators and adjusting the phase difference. CONSTITUTION:The phase difference of 1st and 2nd timing signals S15, S25 is outputted as counting results S17, S27. When the signal S25 is delayed more than the signal S15, comparator circuits 15, 25 output comparison result signals S18, S28. A delay circuit 16 receives the signals S17, S27 to give a delay to a reference signal S16 and th signal S15 and outputs the results as a reference signal S101 and a timing signal S19. On the other hand, a delay circuit 26 receives the signals S27, S28 and gives no delay to a reference signal S16 and the signal S25 and outputs the result as a reference signal 201 and a timing signal S29. Consequently, a phase difference between the reference signals and between the timing signals due to a phase error in voltage controlled oscillators 13, 23 is eliminated. Thus, the reference signal and the timing signal having a redundant system without a phase difference are supplied to the device.
申请公布号 JPH0614013(A) 申请公布日期 1994.01.21
申请号 JP19920168060 申请日期 1992.06.26
申请人 NEC CORP 发明人 KARASHIMA YUKIE
分类号 G06F1/04;H04L1/22;H04L7/00 主分类号 G06F1/04
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