| 摘要 |
<p>PURPOSE:To provide a digital filter which can suppress the increase of the number of gates and can reduce the number of multiplier circuits by adding together two pieces of data so as to secure the same addition value of the input sequence among 2M pieces of continuous data and then multiplying and accumulating the coefficients. CONSTITUTION:The data which are continuous in the input order are outputted from the bit Q7 output of a register 6 as an odd order number output, and the data 4 bits (N bits) later than the immediately precedent data of an odd order number are outputted from the bit Q7 output as an even order number output. Meanwhile the data which are continuous in the order opposite to the input order in terms of an odd order number are outputted from a bit Q8 of a register 10 as the data which are one bit older than the first data of the bit Q7 output of the first register 6. Then the data 4 bits (N bits) older than the immediately precedent data of an odd order number are outputted from the bit Q8 of an even order number. When the output of data of 8 bits (M bits) is complete through both registers 6 and 10, the same operation is applied by M bits to the data advanced by N bits. In such a way, the multiplying frequency can be halved and also the number of gates can be decreased.</p> |
