| 摘要 |
PURPOSE: To reduce parasitic capacity by providing emitter layers which are electrically brought into contact with a 1st epitaxial semiconductor region and separated from each other with effective channel length of a specific width in its lateral direction and providing a barrier layer and a 3rd epitaxial semiconductor layer with a collector layer, having a specific width in the lateral direction. CONSTITUTION: Emitter contact layers 12, 13 on the 1st epitaxial semiconductor layer 14 are patterned, so that a recessed shape 61 having width Lch (Lch <=5μm) in the lateral direction divides the layers 12, 13. Oblong mesa-type structure 20 having 50μm lateral width W is formed and pattern, so as to have a 3rd epitaxial semiconductor layer (multi-layer structure collector) 16. In a trench, only the emitter layer in the two emitter contact layers 12, 13 are penetrated, electrically connected, and face directly opposite the mesa-type structure 20. Since an interval Lc between the layers 31, 32 is >=Lch and the width of the structure 20 is >=Lch and <=Lc , parasitic capacitance can be obtained.
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