发明名称 BUFFER CONTROL SYSTEM
摘要 PURPOSE:To convert the address of a large scale with a small scale table by setting plural areas including a prescribed number of blocks to a buffer memory and designating a relative position in the area of the block for storing data and one of the areas while making a part of addresses of information blocks correspond to other parts. CONSTITUTION:Addresses Ad1, Ad2 at upper and lower digits of an address Ad of an input packet are inputted to conversion sections 31, 32 via buses 51, 52 corresponding respectively to each other. The conversion sections 31, 32 hold the position information of a block and a head address Ad in a corresponding area of a memory 1 storing the Ad1, Ad2 as a relative address from the position of the head address. Memory area and memory block control sections 41, 42 control each area on the memory 1 and the presence of the use of each block. Furthermore, the management sections 41, 42 allocate non-use area with a designation request and writes the result to Ad1, Ad2 conversion tables and output the address and data to the table. Thus, the address conversion with a large scale is attained by using a small scale table.
申请公布号 JPH0614060(A) 申请公布日期 1994.01.21
申请号 JP19920192741 申请日期 1992.06.29
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YOSHIBA HARUMINE
分类号 G06F12/00;H04L12/879;H04L12/951;H04L13/08 主分类号 G06F12/00
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